The present invention relates to an improved power stage with increased output dynamics.
In particular, the invention relates to a power stage having the simplified layout illustrated in FIG. 1, comprising a power amplifier 1 having an inverting input 2, a non-inverting input 3 and an output 4 to be connected to a load R.sub.L. The stage furthermore comprises a feedback network comprising a resistor R.sub.2 connected between the inverting input 2 and the output 4 and a second resistor R.sub.1 connected, with a first terminal, to the inverting input 2 and, with a second terminal, to a first reference voltage (in this case the ground) through a reference voltage source V.sub.R. The non-inverting input 3 of the amplifier 1 receives the signal to be amplified V.sub.i raised with respect to the ground by the reference voltage V.sub.R. The figure furthermore illustrates the biasing currents I+, I- respectively of the non-inverting input 3 and of the inverting input 2.
If no signal is applied (i.e. when V.sub.i =0) the output voltage V.sub.o is equal to the reference voltage V.sub.R which, in the applications in which a single power supply line is used, such as the one illustrated in FIG. 1, is equal to half of the supply voltage.
If the biasing currents I+, I- can be considered negligible, the output signal V.sub.o is a function of the input signal V.sub.i according to the expression: ##EQU1##
When the open-loop gain of the stage is not sufficiently high, or with a particular circuital configuration (as will become apparent in the exemplifying circuit described hereafter) if the load absorbs a high-value current I.sub.o the biasing currents I+,I- may have appreciable values. Relation (1) is consequently no longer a good approximation of the real behavior of the power stage. In this case, in particular, the dynamic characteristics of the amplifier are reduced considerably. The possibility of saturating the transistors comprised in the power stage is limited, this limitation being relatively onerous, since in power applications the condition that the transistors must operate in saturation is often forced.
In fact, if V.sub.M defines the highest value attainable by the inverting terminal of the amplifier, the maximum current which can flow through the resistor R.sub.1 is naturally given by: ##EQU2## if the condition: ##EQU3## is met; ignoring the current flowing through the resistor R.sub.2 and designating I.sub.sat the input biasing current in saturation, the stage cannot sustain the saturated output towards the more positive voltage. The same is true for the saturation for the more negative voltage.
This problem is particularly apparent when low power supply voltages are used in battery-operated systems.
In order to clarify this concept, reference should be made to the exemplifying circuit illustrated in FIG. 2, showing an operational power amplifier as disclosed in the U.S. patent application No. 180,742 filed on Apr. 12, 1988 in the name of the same Applicant. Said operational power amplifier allows a high dynamics of the output signal, which can approach the power supply voltages less the drop V.sub.CE,sat on the output transistor Q.sub.1 or Q.sub.1 ' in saturation.
The circuit illustrated in FIG. 2 comprises, in a conventional manner, a differential input stage 10, an amplifier 11 with gain -A, a buffer stage 12 and the power output stage 13. As the input stage 10 and the amplifier 11 are fully conventional and their description is not important for understanding the operation of the circuit, they are not described. The buffer stage 12 and the output stage 13 are instead illustrated in greater detail. The latter is equivalent to the simplified diagram illustrated in FIG. 1, so that the same reference numerals have been used. As can be seen, the buffer stage 12 comprises a pair of transistors 15, 16 fed by respective current sources I.sub.15, I.sub.16 adapted to drive respectively the lower stage 17 and the upper stage 18 of the power output section 13. Each stage 17, 18 (with particular reference to the upper one 18) comprises a pair of driving transistors Q.sub.3, Q.sub.4 for driving the output power transistor Q.sub.1. A further transistor Q.sub.2 has its emitter connected to the bases of the transistors Q.sub.1, Q.sub.3 and its base connected to the collector of Q.sub.3 so as to recover the base current of the output power transistor Q.sub.1. The figure also illustrates the feedback network constituted by the resistor R.sub.1, which has one terminal connected to the reference voltage V.sub.R and its other terminal connected to the emitter of the transistor Q.sub.4 (point V-), and by the resistor R.sub.2 connected between the point V- and the output having the voltage V.sub.o. The circuit furthermore comprises the resistors R and R' connected between the emitter and the base of Q.sub.3 and the power supply V.sub.CC.
Regarding the operation, consider the case in which the output V.sub.o tends to the more positive voltage; the following description can be obviously repeated symmetrically if the output tends to the more negative voltage. From the analysis of FIG. 2 it is obvious to the man skilled in the art that the current I+ does not create excessive problems provided that the current source I.sub.16 is adequately dimensioned. The issue is different for the current I-, which is equal to the sum of I.sub.1, (the current flowing through the transistor Q.sub.3), and of I.sub.2, (the base current of the transistor Q.sub.2). In correct operating conditions said current I- must flow entirely through the resistor R.sub.1. By inspecting the network it can be stated that the maximum value V.sub.MAX of the voltage at the inverting terminal V- is approximately: EQU V.sub.MAX .perspectiveto.V.sub.CC -V.sub.BE1,sat -V.sub.BE2 -V.sub.CE4,sat
wherein V.sub.BE1,sat is the base-emitter voltage drop of Q.sub.1 in saturation, V.sub.BE2 is the base-emitter voltage drop of Q.sub.2, and V.sub.CE4,sat is the collector-emitter voltage drop of the transistor Q.sub.4 in saturation.
Assuming that EQU V.sub.R =V.sub.CC /2
the maximum current which can flow through the resistor R.sub.1 is given by: ##EQU4##
For supply voltages comprised between 3 and 4 V the numerator of (2) becomes a very small voltage.
In order to obtain the required operation in saturation it is therefore necessary to force the following condition: EQU I.sub.MAX .gtorsim.I.sub.sat
to obtain the saturation of Q.sub.4.
Various solutions are known for satisfying this condition.
In particular, a first solution keeps the value of R.sub.1 and therefore of R.sub.2 sufficiently low. This solution however is disadvantageous since it entails a high current consumption of the stage in saturation conditions.
Another solution makes the emitter junction area of the transistor Q.sub.2 large enough to reduce the weight of the current I.sub.2. However, this solution, is disadvantageous too, due to the considerable increase in the dimensions of the integrated circuit.
Another solution gives the degeneration resistor R a sufficiently high value or increases the area ratio of the emitter junctions of the transistors Q.sub.1 and Q.sub.3 to reduce the weight of the current I.sub.1. However, this solution is disadvantageous too, since the rest current flowing through the power transistors in output becomes very high, increasing thus their dissipation.
A final solution keeps the reference voltage V.sub.R at a value lower than V.sub.CC /2. However, this solution, too, is not advantageous due to the asymmetries which occur in the operation of the circuit.